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cy8c21334, cy8c21534 automotive psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-12550 rev. *h revised january 31, 2011 features automotive electronics council (aec) q100 qualified powerful harvard-architecture processor ? m8c processor speeds up to 24 mhz ? low power at high speed ? operating voltage: 3.0 v to 5.25 v ? automotive temperature range: ?40 c to +85 c advanced peripherals (psoc ? blocks) ? four analog ty pe e psoc blocks provide: ? two comparators with digital-to-analog converter (dac) references ? up to 10-bit single or dual, 24 channel analog-to-digital converters (adc) ? four digital psoc blocks provide: ? 8- to 32-bit timers, counters , and pulse width modulators (pwms) ? cyclical redundancy check (crc) and pseudo-random sequence (prs) modules ? full- or half-duplex uart ? spi master or slave ? connectable to all general purpose i/o (gpio) pins ? complex peripherals by combining blocks ? capacitive sensing application capability flexible on-chip memory ? 8 kb flash program storage ? 512 bytes sram data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software (psoc designer?) ? full-featured in-circuit em ulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory precision, programmable clocking ? internal 5% 24 mhz oscillator ? internal low-speed, low-power oscillator for watchdog and sleep functionality ? optional external oscillator, up to 24 mhz programmable pin configurations ? 25 ma sink, 10 ma drive on all gpios ? pull-up, pull-down, high z, strong, or open drain drive modes on all gpios ? analog input on all gpios ? configurable interrupt on all gpios versatile analog mux ? common internal analog bus ? simultaneous connection of i/o combinations additional system resources ? inter-integrated circuit (i 2 c?) master, slave, or multi-master operation up to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection (lvd) ? integrated supervisory circuit ? on-chip precision voltage reference logic block diagram [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 2 of 37 contents psoc functional overview .............................................. 3 the psoc core ........................................................... 3 the digital system ...................................................... 3 the analog system ..................................................... 4 additional system resources ..................................... 4 psoc device characteristics . ..................................... 5 getting started .................................................................. 5 application notes ........................................................ 5 development kits ........................................................ 5 training ....................................................................... 5 cypros consultants .................................................... 5 solutions library .......................................................... 5 technical support ....................................................... 5 development tools .......................................................... 6 psoc designer software subsyst ems .......... .............. 6 designing with psoc designer ....................................... 7 select components ..................................................... 7 configure components .......... .............. .............. ......... 7 organize and connect .............. .............. ........... ......... 7 generate, verify, and debug ....................................... 7 pinouts .............................................................................. 8 20-pin part pinout ...................................................... 8 28-pin part pinout ....................................................... 9 registers ......................................................................... 10 register conventions ................................................ 10 register mapping tables .......................................... 10 electrical specifications ................................................ 13 absolute maximum ratings ... .................................... 14 operating temperature ............................................. 14 dc electrical characteristics ..................................... 15 ac electrical characteristics ..................................... 18 packaging information ................................................... 23 packaging dimensions .............................................. 23 thermal impedances ................................................ 24 solder reflow peak temperat ure ............................. 24 tape and reel information .... .............. .............. ........ 25 development tool selection .. .............. .............. ........... 27 software .................................................................... 27 development kits ...................................................... 27 evaluation tools ........................................................ 27 device programmers ............. .................................... 28 accessories (emulation and programming) .............. 28 ordering information ...................................................... 29 ordering code definitions ..... .................................... 29 reference information ................................................... 30 acronyms .................................................................. 30 reference documents ............................................... 30 document conventions ......... .................................... 31 glossary .................................................................... 31 document history page ................................................. 36 sales, solutions, and legal information ...................... 37 worldwide sales and design s upport ......... .............. 37 products .................................................................... 37 psoc solutions ......................................................... 37 [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 3 of 37 psoc functional overview the psoc family consists of many devices with on-chip controllers. these devices are designed to replace multiple traditional microcontroller unit (mcu)-based system components with one, low-cost single-chip programmable component. a psoc device includes configurable blocks of analog and digital logic, and programmable interconnect. this architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the psoc architecture, as illustrated in the ?logic block diagram? on page 1, comprises of four main areas: the core, the system resources, the digita l system, and the analog system. configurable global bus resources allow all the device resources to be combined into a complete custom system. each cy8c21x34 psoc device includes four digital blocks and four analog blocks. depending on the psoc package, up to 24 gpios are also included. the gpios provide access to the global digital and analog interconnects. the psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep, and watchdog timers, and an internal main oscillator (imo) and internal low-speed oscillator (ilo). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four-million instructions per second (mips) 8-bit harvard-architecture microprocessor. system resources provide additional capability, such as digital clocks for increas ed flexibility, i 2 c functionality for implementing an i 2 c master, slave, or multi-master, an internal voltage reference that provides an absolute value of 1.3 v to a number of psoc subsystems, and various system resets supported by the m8c. the digital system is composed of an array of digital psoc blocks, which can be configured into any number of digital peripherals. the digital blocks can be connected to the gpio through a series of global buses that can route any signal to any pin. this frees designs from the constraints of a fixed peripheral controller. the analog system is composed of four analog psoc blocks, supporting comparators and analog-to-digital conversion with up to 10 bits of precision. the digital system the digital system is composed of four digital psoc blocks. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16- , 24-, and 32-bi t peripherals, which are called user modules. digital peripheral configurations include those listed. pwms (8- to 32-bit) pwms with dead band (8- to 24-bit) counters (8- to 32-bit) timers (8- to 32-bit) full or half-duplex 8-bit uart with selectable parity spi master and slave i 2 c master, slave, or multi-mast er (implemented in a dedicated i 2 c block) cyclical redundancy checker/generator (16-bit) infrared data association (irda) prs generators (8- to 32-bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. figure 1. digital system block diagram digital blocks are provided in rows of four, where the number of blocks varies by psoc device family. this allows you the optimum choice of system resource s for your application. family resources are shown in ta b l e 1 on page 5. digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 3 port 2 port 1 port 0 [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 4 of 37 the analog system the analog system is composed of four configurable blocks, allowing the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the common psoc analog functions for this device (most available as user modules) are listed. adcs (single or dual, with up to 10-bit resolution) pin-to-pin comparator single-ended comparators (up to two) with absolute (1.3 v) reference or 8-bit dac reference 1.3 v reference (as a system resource) in most psoc devices, analog blocks are provided in columns of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks. the cy8c 21x34 devices pr ovide limited functionality type e analog blocks. each co lumn contains one ct type e block and one sc type e block. refer to the psoc programmable system-on-chip technical reference manual for detailed information on the cy8c 21x34?s type e analog blocks. figure 2. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin. pins can be connected to the bus individual ly or in any combination. the bus also connects to the analog system for analysis with comparators and adcs. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. switch-control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications such as touch sensing. other multiplexer applications include: track pad, finger sensing. chip-wide mux that allows analog input from any i/o pin. crosspoint connection between any i/o pin combination. additional system resources system resources, some of whic h have been previously listed, provide additional capability us eful for complete systems. brief statements describing the merits of each system resource are presented. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. the i 2 c module provides communication up to 400 khz over two wires. slave, master, and multi-master modes are all supported. lvd interrupts can signal the application of falling voltage levels, while the advanced power-on reset (por) circuit eliminates the need for a system supervisor. an internal 1.3 v voltage reference provides an absolute reference for the analog system, including adcs and dacs. versatile analog mu ltiplexer system. acol1mux ace00 ace01 array array input configuration ase10 ase11 analog mux bus all io aci0[1:0] aci1[1:0] from port 0 [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 5 of 37 psoc device characteristics depending on your psoc device characteri stics, the digital and analog systems can have a varying number of digital and analog blocks. table 1 lists the resources available for specif ic psoc device groups. the psoc device co vered by this datasheet is highlighted in ta b l e 1 getting started for in-depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size cy8c29x66 [1] up to 64 4 16 up to 12 4 4 12 2 k 32 k cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [2] 1 k 16 k cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k cy8c24x94 [1] up to 56 1 4 up to 48 2 2 6 1 k 16 k cy8c24x23a [1] up to 24 1 4 up to 12 2 2 6 256 4 k cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k cy8c22x45 [1] up to 38 2 8 up to 38 0 4 6 [2] 1 k 16 k cy8c21x45 [1] up to 24 1 4 up to 24 0 4 6 [2] 512 8 k cy8c21x34 [1] up to 28 1 4 up to 28 0 2 4 [2] 512 8 k cy8c21x23 up to 16 1 4 up to 8 0 2 4 [2] 256 4 k cy8c21x12 [ 1 ] up to 24 1 1 [ 2 ] 24 0 0 1 [ 2 ] 512 8 k cy8c20x34 [1] up to 28 0 0 up to 28 0 0 3 [2,3] 512 8 k cy8c20xx6 up to 36 0 0 up to 36 0 0 3 [2,3] up to 2 k up to 32 k notes 1. automotive qualified devices available in this group. 2. limited analog functionality. 3. two analog blocks and one capsense ? block. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 6 of 37 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/transmitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are adcs, dacs, amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project wit h apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows you to create a trac e buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-s ensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulat ion pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 7 of 37 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process can be summarized in the following four steps: 1. select user modules 2. configure user modules 3. organize and connect 4. generate, verify, and debug select components psoc designer provides a library of pre-built, pre-tested hardware peripheral components called "user modules." user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure components each of the user modules you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your part icular application. for example, a pwm user module configures one or more digital psoc blocks, one for each 8 bits of resolu tion. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-dow n menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the "generate configuration files" step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface prov ides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 8 of 37 pinouts the cy8c21x34 psoc device is available in a variety of package s which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital i/o and connection to the common analog bus. however, v ss , v dd , and xres are not capable of digital i/o. 20-pin part pinout table 2. 20-pin part pinout (s hrink small-outline package (ssop)) pin no. type name description figure 3. cy8c21334 20-pin psoc device digital analog 1 i/o i, m p0[7] analog column mux input 2 i/o i, m p0[5] analog column mux input 3 i/o i, m p0[3] analog column mux input, c mod capacitor pin 4 i/o i, m p0[1] analog column mux input, c mod capacitor pin 5 power v ss ground connection 6 i/o m p1[7] i 2 c serial clock (scl) 7 i/o m p1[5] i 2 c serial data (sda) 8 i/o m p1[3] 9 i/o m p1[1] i 2 c scl, issp-sclk [4] 10 power v ss ground connection 11 i/o m p1[0] i 2 c sda, issp-sdata [4] 12 i/o m p1[2] 13 i/o m p1[4] optional external clock input (extclk) 14 i/o m p1[6] 15 input xres active high external reset with internal pull-down 16 i/o i, m p0[0] analog column mux input 17 i/o i, m p0[2] analog column mux input 18 i/o i, m p0[4] analog column mux input 19 i/o i, m p0[6] analog column mux input 20 power v dd supply voltage legend a = analog, i = input, o = output, and m = analog mux input. ssop 1 ai, m, p0[7] ai, m, p0[5] ai, m, p0[3] ai, m, p0[1] i2c scl, m, p1[7] i2c sda, m, p1[5] m, p1[3] i2c scl, m, p1[1] v ss 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd p0[6], m, ai p0[4], m, ai p0[2], m, ai p0[0], m, ai xres p1[6], m p1[4], m, extclk p1[2], m p1[0], m, i2c sda v ss note 4. these are the issp pins, which are not high z when coming out of por. see the psoc technical reference manual for details. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 9 of 37 28-pin part pinout note 5. these are the issp pins, which are not high z when coming out of por. see the psoc technical reference manual for details. table 3. 28-pin part pinout (ssop) pin no. type name description figure 4. cy8c21534 28-pin psoc device digital analog 1 i/o i, m p0[7] analog column mux input 2 i/o i, m p0[5] analog column mux input 3 i/o i, m p0[3] analog column mux input, c mod capacitor pin 4 i/o i, m p0[1] analog column mux input, c mod capacitor pin 5 i/o m p2[7] 6 i/o m p2[5] 7 i/o m p2[3] 8 i/o m p2[1] 9 power v ss ground connection 10 i/o m p1[7] i 2 c scl 11 i/o m p1[5] i 2 c sda 12 i/o m p1[3] 13 i/o m p1[1] i 2 c scl, issp-sclk [5] 14 power v ss ground connection 15 i/o m p1[0] i 2 c sda, issp-sdata [5] 16 i/o m p1[2] 17 i/o m p1[4] optional extclk 18 i/o m p1[6] 19 input xres active high external reset with internal pull-down 20 i/o m p2[0] 21 i/o m p2[2] 22 i/o m p2[4] 23 i/o m p2[6] 24 i/o i, m p0[0] analog column mux input 25 i/o i, m p0[2] analog column mux input 26 i/o i, m p0[4] analog column mux input 27 i/o i, m p0[6] analog column mux input 28 power v dd supply voltage legend a = analog, i = input, o = output, and m = analog mux input. ssop 1 ai, m, p0[7] ai, m, p0[5] ai, m, p0[3] ai, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] v ss i2c scl, m, p1[7] i2c sda, m, p1[5] m, p1[3] i2c scl, m, p1[1] v ss 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v dd p0[6], m, ai p0[4], m, ai p0[2], m, ai p0[0], m, ai p2[6], m p2[4], m p2[2], m p2[0], m xres p1[6], m p1[4], m, extclk p1[2], m p1[0], m, i2c sda [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 10 of 37 registers register conventions this section lists the registers of the cy8c21x34 psoc device. for detailed register information, refer to the psoc technical reference manual . the register conventions specific to this section are listed in the following table. register mapping tables the psoc device has a total register address space of 512 bytes. the register space is re ferred to as i/o space and is divided into two banks, bank 0 and bank 1. the xio bit in the flag register (cpu_f) determines which bank the user is currently in. when the xio bit is set to ?1?, the user is in bank 1. note in the following register mapping tables, blank fields are reserved and must not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 11 of 37 table 4. register map 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 cur_pp d0 rw 11 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amux_cfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbb00cr0 23 # 63 a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 e4 dbb01dr1 25 w 65 a5 e5 dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # adc0_cr 68 # a8 e8 dcb02dr1 29 w adc1_cr 69 # a9 e9 dcb02dr2 2a rw 6a aa ea dcb02cr0 2b # 6b ab eb dcb03dr0 2c # tmp_dr0 6c rw ac ec dcb03dr1 2d w tmp_dr1 6d rw ad ed dcb03dr2 2e rw tmp_dr2 6e rw ae ee dcb03cr0 2f # tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 12 of 37 table 5. register map 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 adc0_tr e5 rw dbb01ou 26 rw amd_cr1 66 rw a6 adc1_tr e6 rw 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b clk_cr3 6b rw ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 13 of 37 electrical specifications this section presents the dc and ac electr ical specifications of the cy8c21x34 psoc device. for the most up-to-date electrical specifications, visit the cypress website at http://www.cypress.com . specifications are valid for ?40 c t a 85 c and t j 100 c as specified, except where noted. refer to table 12 on page 18 for the electrical specifications for t he imo using slow imo (slimo) mode. figure 5. voltage versus cpu frequency figure 6. imo frequency trim options 5.25 4.75 93 khz 24 mhz cpu frequency (nominal setting) v dd voltage (v) 0 12 mhz 3.0 v a l i d o p e r a t in g r e g i o n slimo mode = 0 slimo mode = 0 slimo mode = 1 5.25 4.75 6 mhz 24 mhz imo frequency 0 12 mhz 3.0 3.6 slimo mode = 1 v dd voltage (v) [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 14 of 37 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested operating temperature symbol description min typ max units notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. time spent in storage at a temperature greater than 65 c counts toward the flashdr electrical specification in table 11 on page 17. t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current in to any port pin ?25 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma symbol description min typ max units notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see thermal impedances on page 24. the user must limit the power consumption to comply with this requirement. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 15 of 37 dc electrical characteristics dc chip level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. dc gpio specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 6. dc chip level specifications symbol description min typ max units notes v dd supply voltage 3.0 ? 5.25 v see table titled dc por and lvd specifi- cations on page 16 i dd supply current, imo = 24 mhz ? 4 6 ma conditions are v dd = 5.25 v, cpu = 3 mhz, 48 mhz disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz i dd3 supply current, imo = 6 mhz using slimo mode ? 2 4 ma conditions are v dd = 3.3 v, cpu = 3 mhz, 48 mhz disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz i sb1 sleep (mode) current with por, lvd, sleep timer, wdt, and ilo active ? 2.8 7 a v dd = 3.3 v, ?40 c t a 85 c i sb2 sleep (mode) current with por, lvd, sleep timer, wdt, and ilo active ? 5 15 a v dd = 5.25 v, ?40 c t a 85 c v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate v dd range table 7. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k r pd pull-down resistor 4 5.6 8 k also applies to the internal pull-down resistor on the xres pin v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])) v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])) i oh high level source current 10 ? ? ma v oh v dd ? 1.0 v, see the limitations of the total current in the note for v oh i ol low level sink current 25 ? ? ma v ol 0.75 v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.8 v v ih input high level 2.1 ? v v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent temp = 25 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent temp = 25 c [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 16 of 37 dc operational amplifier specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. dc analog mux bus specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. dc por and lvd specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 8. dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/ c i eboa [6] input leakage current (port 0 analo g pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent te m p = 2 5 c v cmoa common mode voltage range 0.0 ? v dd ? 1 v g oloa open loop gain ? 80 ? db i soa supply current 3.0 v v dd 3.6 v ? 30 ? a 4.75 v v dd 5.25 v ? 35 ? a notes 6. atypical behavior: i eboa of port 0 pin 0 is below 1 na at 25 c; 50 na over temperature. use port 0 pins 1-7 for the lowest leakage of 200 pa. 7. always greater than 50 mv above v ppor1 (porlev[1:0] = 01b) for falling supply. table 9. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 r vdd resistance of initialization switch to v dd ? ? 800 table 10. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 v dd value for precision por (ppor) trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v v dd must be greater than or equal to 2.5 v during startup, reset from the xres pin, or reset from watchdog. v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.99 [7] 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v v [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 17 of 37 dc programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 11. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 3.0 3.1 3.2 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operation 3.0 ? 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor v olv output low voltage during programming or verify ? ? 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) [8, 9] 1,000 ? ? ? erase/write cycles per block flash ent flash endurance (total) [9, 10] 128,000 ? ? ? erase/write cycles flash dr flash data retention 15 ? ? years notes 8. the erase/write cycle limit per block (flash enpb ) is only guaranteed if the device operates within one voltage range. voltage ranges are 3.0 v to 3.6 v and 4.75 v to 5.25 v. 9. for the full temperature range, the user must employ a temper ature sensor user module (flashtemp) or other temperature sensor , and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 for more information. 10. the maximum total number of allowed erase/write cycles is the minimum flash enpb value multiplied by the number of flash blocks in the device. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 18 of 37 ac electrical characteristics ac chip level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 12. ac chip level specifications symbol description min typ max units notes f imo24 imo frequency for 24 mhz 22.8 [11] 24 25.2 [11] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 6 on page 13. slimo mode = 0. f imo6 imo frequency for 6 mhz 5.5 [11] 6 6.5 [11] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 6 on page 13. slimo mode = 1. f cpu1 cpu frequency (5 v v dd nominal) 0.089 [11] 24 25.2 [11] mhz 24 mhz only for slimo mode = 0 f cpu2 cpu frequency (3.3 v v dd nominal) 0.089 [11] 12 12.6 [11] mhz f blk5 digital psoc block frequency 0 (5 v v dd nominal) 0 48 50.4 [11,12] mhz refer to the ac digital block specifications below f blk33. digital psoc block frequency (3.3 v v dd nominal) 0 24 25.2 [11, 12] mhz refer to the ac digital block specifications below f 32k1 ilo frequency 15 32 64 khz this specification applies when the ilo has been trimmed f 32ku ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c processor starts to execute, the ilo is not trimmed. t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 45.6 [11] 48.0 50.4 [11] mhz f max maximum frequency of signal on row input or row output ? ? 12.6 mhz sr powerup power supply slew rate ? ? 250 v/ms v dd slew rate during power-up t powerup time between end of por state and cpu code execution ? 16 100 ms power-up from 0 v. t jit_imo [13] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 700 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 900 ps n = 32 24 mhz imo period jitter (rms) ? 100 400 ps notes 11. accuracy derived from imo with appropriate trim for v dd range. 12. see the individual user module datasheets for information on maximum frequencies for user modules. 13. refer to cypress jitter specifications application note, understanding datasheet jitter specificat ions for cypress timing products ? an5054 for more information. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 19 of 37 ac gpio specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. figure 7. gpio timing diagram ac operational amplifier specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 13. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.6 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 2 6 18 ns v dd = 4.75 to 5.25 v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 2 6 18 ns v dd = 4.75 to 5.25 v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 7 27 ? ns v dd = 3 to 5.25 v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 7 22 ? ns v dd = 3 to 5.25 v, 10% to 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage table 14. ac operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time, 50 mv overdrive ? 75 100 ns [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 20 of 37 ac digital block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 15. ac digital block specifications function description min typ max units notes all functions block input clock frequency v dd 4.75 v ? ? 50.4 [15] mhz v dd < 4.75 v ? ? 25.2 [15] mhz timer input clock frequency no capture, v dd 4.75 v ? ? 50.4 [15] mhz no capture, v dd < 4.75 v ? ? 25.2 [15] mhz with capture ? ? 25.2 [15] mhz capture pulse width 50 [14] ??ns counter input clock frequency no enable input, v dd 4.75 v ? ? 50.4 [15] mhz no enable input, v dd < 4.75 v ? ? 25.2 [15] mhz with enable input ? ? 25.2 [15] mhz enable input pulse width 50 [14] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [14] ??ns disable mode 50 [14] ??ns input clock frequency v dd 4.75 v ? ? 50.4 [15] mhz v dd < 4.75 v ? ? 25.2 [15] mhz crcprs (prs mode) input clock frequency v dd 4.75 v ? ? 50.4 [15] mhz v dd < 4.75 v ? ? 25.2 [15] mhz crcprs (crc mode) input clock frequency ? ? 25.2 [15] mhz spim input clock frequency ? ? 8.4 [15] mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.2 [15] mhz the input clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [14] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd 4.75 v, 2 stop bits ? ? 50.4 [15] mhz v dd 4.75 v, 1 stop bit ? ? 25.2 [15] mhz v dd < 4.75 v ? ? 25.2 [15] mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd 4.75 v, 2 stop bits ? ? 50.4 [15] mhz v dd 4.75 v, 1 stop bit ? ? 25.2 [15] mhz v dd < 4.75 v ? ? 25.2 [15] mhz notes 14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). 15. accuracy derived from imo with appropriate trim for v dd range. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 21 of 37 ac external clock specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. ac programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. table 16. 5-v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power-up imo to switch 150 ? ? s table 17. 3.3-v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ? s table 18. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns t sclk frequency of sclk 0 ? 8 mhz t eraseb flash block erase time ? 10 40 [16] ms t write flash block write time ? 40 160 [16] ms t dsclk data out delay from falling edge of sclk ? 38 45 ns 3.6 < v dd t dsclk3 data out delay from falling edge of sclk ? 44 50 ns 3.0 v dd 3.6 t prgh total flash block program time (t eraseb + t write ), hot ? ? 100 [16] ms t j 0 c t prgc total flash block program time (t eraseb + t write ), cold ? ? 200 [16] ms t j < 0 c note 16. for the full temperature range, the user must employ a temperature sensor user module (flashtemp) or other temperature senso r, and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 for more information. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 22 of 37 ac i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters apply to 5 v or 3.3 v at 25 c and are for design guidance only. figure 8. definition for timing for fast/standard mode on the i 2 c bus table 19. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 [17] 0400 [17] khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ?100 [18] ?ns t sustoi2c setup time for st op condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition notes 17. f scli2c is derived from sysclk of the psoc. this specification assumes that sysclk is operating at 24 mhz, nominal. if sysclk is at a lower frequency, then the f scli2c specification adjusts accordingly 18. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudati2c 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signa l. if such device does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax +t sudati2c = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 23 of 37 packaging information this section illustrates the packaging spec ifications for the cy8c21x34 psoc device, along with the thermal impedances for each package. important note emulation tools may require a larger area on the target pc b than the chip's footprint. for a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com . packaging dimensions figure 9. 20-pin (210-mil) ssop 51-85077 *d [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 24 of 37 figure 10. 28-pin (210-mil) ssop thermal impedances solder reflow peak temperature ta b l e 2 1 shows the solder reflow temperature limits that need to be met for preventing device damage. 51-85079 *d table 20. thermal impedances per package package typical ja [19] typical jc 20-pin ssop 117 c/w 41 c/w 28-pin ssop 96 c/w 39 c/w note 19. t j = t a + power x ja table 21. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature 20-pin ssop 260 c 20 s 28-pin ssop 260 c 20 s [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 25 of 37 tape and reel information figure 11. 20-pin ssop carrier tape drawing 51-51101 *a [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 26 of 37 figure 12. 28-pin ssop carrier tape drawing table 22. tape and reel specifications package cover tape width (mm) hub size (inches) minimum leading empty pockets minimum trailing empty pockets standard full reel quantity 20-pin ssop 13.3 4 42 25 2000 28-pin ssop 13.3 7 42 25 1000 51-51100 *b [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 27 of 37 development tool selection this section presents the development tools available for the cy8c21x34 family. software psoc designer at the core of the psoc development software suite is psoc designer. utilized by thousan ds of psoc developers, this robust software has been facilitating psoc designs for years. psoc designer is available free of charge at http://www.cypress.com. psoc designer comes with a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits can be purchased from the cypress online store . the online store also has the most up-to-date information on kit contents, descriptions, and availability. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation, and the software interface allows you to run, halt, and single step the processor, and view the contents of specific memory locations. advanced emulation features are also supported through psoc designer. the kit includes: ice-cube unit 28-pin pdip emulation pod for cy8c29466-24pxi two 28-pin cy8c29466-24pxi pdip psoc device samples psoc designer software cd issp cable minieval socket programming and evaluation board backward compatibility cable (for connecting to legacy pods) universal 110/220 power supply (12 v) european plug adapter usb 2.0 cable getting started guide development kit registration form cy3280-bk1 the cy3280-bk1 universal capsense control kit is designed for easy prototyping and debug of capsense designs with pre-defined control circuitry and plug-in hardware. the kit comes with a control boards for cy8c20x34 and cy8c21x34 devices as well as a breadboard module and a button(5)/slider module. evaluation tools all evaluation tools can be purchased from the cypress online store . cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, an rs-232 port, and plenty of breadboarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit two 28-pin cy8c29466-24pxi pdip psoc device samples psoc designer software cd getting started guide usb 2.0 cable cy3235-proxdet the cy3235 capsense proximity detection demonstration kit allows quick and easy demonstration of a psoc capsense-enabled device (cy8c21x34) to accurately sense the proximity of a hand or finger along the length of a wire antenna. the kit includes: proximity detection demo board w/antenna i2c to usb debugging/communication bridge usb cable (6 feet) supporting software cd cy3235-proxdet quick start guide one cy8c24894 psoc device on i2c-usb bridge one cy8c21434 psoc device on proximity detection demo board cy3210-21x34 evaluation pod (evalpod) the cy3210-21x34 psoc evalpods are pods that connect to the ice in-circuit emulator ( cy3215-dk kit) to allow debugging capability. they can also function as a standalone device without debugging capability. the evalpod has a 28-pin dip footprint on the bottom for easy connection to development kits or other hardware. the top of the evalpod has prototyping headers for easy connection to the device's pins. cy3210-21x34 provides evaluation of the cy8c21x34 psoc device family. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 28 of 37 device programmers all device programmers can be purchased from the cypress online store . cy3210-miniprog1 the cy3210-miniprog1 kit allows a user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs special software and is not compatible with psoc programmer. this software is free and can be downloaded from http://www.cypress.com . the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, european plug adapter usb 2.0 cable accessories (emula tion and programming) table 23. emulation and programming accessories part number pin package pod kit [20] foot kit [21] adapter [22] CY8C21334-24PVXA 20-pin ssop cy3250-21x34 cy3250-20ssop-fk adapters are available at http://www.emulation.com. cy8c21534-24pvxa 28-pin ssop cy3250-21x34 cy3250-28ssop-fk notes 20. pod kit contains an emulation pod, a flex-cable (connects the pod to t he ice), two feet, and device samples. 21. foot kit includes surface mount feet that can be soldered to the target pcb. 22. programming adapter converts non-dip package to dip footprint. sp ecific details and ordering information for each of the ada pters are available at http://www.emulation.com . [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 29 of 37 ordering information the following table lists the cy8c21x34 psoc device?s key package features and ordering codes. ordering code definitions table 24. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) temperature range digital blocks analog blocks digital i/o pins analog inputs analog outputs xres pin 20-pin (210-mil) ssop CY8C21334-24PVXA 8 k 512 ?40 c to +85 c 4 4 16 16 0 yes 20-pin (210-mil) ssop (tape and reel) CY8C21334-24PVXAt 8 k 512 ?40 c to +85 c 4 4 16 16 0 yes 28-pin (210-mil) ssop cy8c21534-24pvxa 8 k 512 ?40 c to +85 c 4 4 24 24 0 yes 28-pin (210-mil) ssop (tape and reel) cy8c21534-24pvxat 8 k 512 ?40 c to +85 c 4 4 24 24 0 yes cy 8 c 21 xxx-24xx package type: thermal rating: px = pdip pb-free a = automotive ?4 0 c to +85 c sx = soic pb-free c = commercial pvx = ssop pb-free i = industrial lfx = qfn pb-free e = automotive extended ?4 0 c to +125 c ax = tqfp pb-free cpu speed: 24 mhz part number family code technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 30 of 37 reference information acronyms ta b l e 2 5 lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywusb6953 psoc ? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash ? an2015 (001-40459) understanding data sheet jitter specifications for cypress timing products ? an5054 (001-14503) table 25. acronyms used in this datasheet acronym description acronym description ac alternating current mips million instructions per second aec automotive electronics council pcb printed circuit board adc analog-to-digital converter pdip plastic dual in-line package api application programming interface pll phase-locked loop cpu central processing unit por power-on reset crc cyclic redundancy check ppor precision power-on reset csd capsense sigma delta prs pseudo-random sequence ct continuous time psoc ? programmable system-on-chip dac digital-to-analog converter pwm pulse width modulator dc direct current or duty cycle sc switched capacitor eeprom electrically erasable programmable read-only memory scl / sclk serial clock extclk external clock sda serial data gpio general-purpose i/o slimo slow internal main oscillator i 2 c inter-integrated circuit smp switch mode pump ice in-circuit emulator soic small-outline integrated circuit ide integrated development environment spi serial peripheral interface ilo internal low-speed oscillator sram static random access memory imo internal main oscillator sr om supervisory read-only memory i/o input/output ssop shrink small-outline package irda infrared data association tqfp thin quad flat pack issp in-system serial programming uart universal asynchronous reciever / transmitter lcd liquid crystal display usb universal serial bus led light-emitting diode wdt watchdog timer lvd low voltage detect xres external reset mcu microcontroller unit [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 31 of 37 document conventions units of measure the following table lists the units of measure that are used in this document. numeric conventions hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?01000011b?). numbers no t indicated by an ?h?, ?b?, or ?0x? are in decimal format. table 26. units of measure symbol unit of measure symbol unit of measure c degree celsius v microvolts db decibels ma milliampere kb 1024 bytes ms millisecond kbit 1024 bits mv millivolts khz kilohertz na nanoampere k kilohm ns nanosecond mbaud megabaud ohm mbps megabits per second pa picoampere mhz megahertz pf picofarad a microampere ps picosecond s microsecond v volts glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opam p circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconn ected to provide adcs, dacs , multi-pole filt ers, gain stages, and much more. analog-to-digital converter (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog converter (dac) performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for prog rammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperature coefficient of vbe, to produce a zero temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 32 of 37 block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for i/o operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and ca rrying similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a common connection for a group of related devices. clock the device that generates a periodic signal with a fi xed frequency and duty cycle. a clock is sometimes used to synchronize different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high level language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allows you to analyze the operation of the system under development. a debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic bl ocks that can act as a counter, timer, serial receiver, serial transm itter, crc generator, pseudo-random number generator, or spi. digital-to-analog converter (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog-to-digital converter (adc) performs the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. glossary (continued) [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 33 of 37 external reset (xres) an active high signal that is driven into the psoc devi ce. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable an d erasable, non-volatile technology that provides you the programmability and data storage of eproms, plus in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconducto rs (now nxp semiconductors). it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building contro l electronics. i2c uses only two bi-directional pins, clock and data, both running at the v dd suppy voltage and pulled high with resistors. the bus operates up to100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces data into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the cpu receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning the device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a typical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls below a sele cted threshold. m8c an 8-bit harvard-architecture microprocessor. the mi croprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is designed pr imarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and i/o circuitry. the reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. glossary (continued) [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 34 of 37 modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or more characteristi cs of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitted data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power-on reset (por) a circuit that forces the psoc device to reset when the volta ge is below a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and progra mmable system-on-chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied value. ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know n state. see hardware reset and software reset. rom an acronym for read only memory. a data-storage devi ce from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to anothe r. shift register a memory storage device that sequentially shifts a wo rd either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. glossary (continued) [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 35 of 37 sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly altered or unt il power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the function s of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is synchronized by a clock signal. tri-state a function whose output can adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be c onsidered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. user modules pre-built, pre-tested hardware/f irmware peripheral functions that take ca re of managing and configuring the lower level analog and digi tal psoc blocks. user module s also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the register s in this bank are more likely to be modified during normal program execution and not just during initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of tim e. glossary (continued) [+] feedback
cy8c21334, cy8c21534 document number: 001-12550 rev. *h page 36 of 37 document history page document title: cy8c21334, cy8c21534 automotive psoc? programmable system-on-chip? document number:001-12550 rev. ecn no. orig. of change submission date description of change ** 646436 hmt see ecn new silicon and document (revision **) *a 2526170 pyrs 07/03/08 corrected ordering information, converted from preliminary to final. *b 2618175 ogne/pyrs 12/09/08 added note in ordering information section. changed title from psoc? mixed-signal array to psoc? programmable system-on-chip? updated ?development tools? and ?designing with psoc designer? sections on pages 5 and 6 *c 2714723 btk/aesa 06/04/09 updated getting started section. replaced designing with user modules section with designing with psoc designer section. updated features list and psoc functional overview section. updated some ac specification values to conform to a 5% accurate imo (no order of magnitude changes). added a note to i2c speci- fications section to clarify the i2c sysclk dependency. added the development tool selection section. deleted some inapplicable or redundant information. changed the title. updated the pdf bookmarks. fixed f imo6 , t rsclk , and t fsclk specifica- tions to be correct. *d 2822792 btk/aesa 12/07/2009 added t prgh, t prgc, i ol , i oh , f 32ku , dc ilo , and t powerup electrical specifica- tions. updated the footnotes for table 11, ?dc programming specifications,? on page 17. added maximum values and updated typical values for t eraseb and t write electrical specifications. replaced t ramp electrical specification with sr powerup electrical specification. added ?sales, solutions, and legal infor- mation? on page 37. this revision fixes cdt 63984. *e 2888007 njf 03/30/2010 updated cypress website links. updated designing with psoc designer . added t baketemp and t baketime parameters in absolute maximum ratings . removed the following sections: dc low power comparator specifications, ac analog mux bus specifications, ac low power comparator specifications, third party tools, and build a psoc emulator into your board. updated links in sales, solutions, and legal information . *f 3023789 btk/aesa 09/06/2010 conversion to new datashee t editing system. merged the 5 v and 3.3 v operational amplifier electrical specifications into the table 8 (with no changes to data). updated datasheet as per cypress style guide and new datasheet template. *g 3094401 3023788 btk 11/23/2010 added tape and reel packaging information. refer to cdt 88767. *h 3157921 btk/njf 01/31/2011 updated i 2 c timing diagram to improve clarity (cdt 92817). updated wording, formatting, and notes of the ac digital block specifications table to improve clarify (cdt 92819). added v ddp , v ddlv , and v ddhv electrical specifications to give more information for programming the device (cdt 92822). updated solder reflow temperature specifications to give more clarity (cdt 92828). updated the jitter specifications (cdt 92831). updated psoc device characteristics table (cdt 92832). updated the f 32ku electrical specification (cdt 92994). updated dc por and lvd specifications to add specs for all por levels (cdt 86716). updated note for r pd electrical specification (cdt 90944). updated reference information section. package diagram spec 51-51100 revised from *a to *b. [+] feedback
document number: 001-12550 rev. *h revised january 31, 2011 page 37 of 37 psoc designer? and programmable system-on-chip? are trademarks and psoc? and capsense? are registered trademarks of cypress sem iconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c21334, cy8c21534 ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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